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型號(hào)：	MQ80C52CXXX-25P883R
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	99/849頁(yè)
文件大?。?/td>	12530K
代理商：	MQ80C52CXXX-25P883R

32099I–01/2012

AT32UC3L016/32/64

The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks

propagate to the digital logic.

The OSCn Ready bit in the Power and Clock Status Register (PCLKSR.OSCnRDY) is set when

the oscillator is stable and ready to be used as clock source. An interrupt can be generated on a

zero-to-one transition on OSCnRDY if the OSCnRDY bit in the Interrupt Mask Register

(IMR.OSCnRDY) is set. This bit is set by writing a one to the corresponding bit in the Interrupt

Enable Register (IER.OSCnRDY).

32KHz Oscillator (OSC32K) Operation

Rev: 1.0.1.1

The 32KHz oscillator operates as described for the oscillator above. The 32 KHz oscillator can

be used as source clock for the Asynchronous Timer (AST) and the Watchdog Timer (WDT).

The 32KHz oscillator can also be used as source for the generic clocks.

The oscillator is disabled by default after reset. When the oscillator is disabled, the XIN32 and

XOUT32 pins can be used as general-purpose I/Os. When the oscillator is enabled, the XIN32

and XOUT32 pins are controlled directly by the SCIF, overriding GPIO settings. When the oscil-

lator is configured to use an external clock, the clock must be applied to the XIN32 pin while the

XOUT32 pin can be used as general-purpose I/O.

The oscillator is enabled writing a one to the OSC32 Enable bit in the 32KHz Oscillator Control

bit, while keeping the other bits unchanged. Writing to OSC32EN while also writing to other bits

may result in unpredictable behavior. Operation mode (external clock or crystal) is selected by

writing to the Oscillator Mode bit in OSCCTRL32 (OSCCTRL32.MODE). The oscillator is an

ultra-low-power design and remains enabled in all sleep modes.

The start-up time of the 32 KHz oscillator is selected by writing to the Oscillator Start-up Time

field in the OSCCTRL32 register (OSCCTRL32.STARTUP). The SCIF masks the oscillator out-

put during the start-up time, to ensure that no unstable clock cycles propagate to the digital logic.

The OSC32 Ready bit in the Power and Clock Status Register (PCLKSR.OSC32RDY) is set

when the oscillator is stable and ready to be used as clock source. An interrupt can be gener-

ated on a zero-to-one transition on PCLKSR.OSC32RDY if the OSC32RDY bit in the Interrupt

Mask Register (IMR.OSC32RDY) is set. This bit is set by writing a one to the corresponding bit

in the Interrupt Enable Register (IER.OSC32RDY).

.As a crystal oscillator usually requires a very long start-up time (up to 1 second), the 32 KHz

oscillator will keep running across resets, except a Power-on Reset (POR).

The 32 KHz oscillator also has a 1 KHz output. This is enabled by writing a one to the Enable

1KHz output bit in OSCCTRL32 register (OSCCTRL32.EN1K). If the 32KHz output clock is not

needed when 1K is enabled, this can be disabled by writing a zero to the Enable 32KHz output

bit in the OSCCTRL32 register (OSCCTRL32.EN32K). OSCCTRL32.EN32K is set after a POR.

The 32 KHz oscillator has two possible sets of pins. To select between them write to the Pin

Select bit in the OSCCTRL32 register (OSCCTRL32.PINSEL). If the 32 KHz oscillator is to be

used in Shutdown mode, PINSEL must be written to one, and XIN32_2 and XOUT32_2 must be

相關(guān)PDF資料	PDF描述
MQ80C52CXXX-25P883R	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
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