![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_799.png)
799
32099I–01/2012
AT32UC3L016/32/64
The maximum SPI slave input frequency is given by the following formula:
Where
is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA.
is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
Where
is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA.
is the
SPI master setup time. Please refer to the SPI master datasheet for
.
is the max-
imum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
32.9.5
TWIM/TWIS Timing
Figure 32-42 shows the TWI-bus timing requirements and the compliance of the device with
them. Some of these requirements (t
r and tf) are met by the device without requiring user inter-
vention. Compliance with the other requirements (t
HD-STA, tSU-STA, tSU-STO, tHD-DAT, tSU-DAT-TWI, tLOW-
TWI, tHIGH, and fTWCK) requires user intervention through appropriate programming of the relevant
TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more
information.
fSPCKMAX
MIN fCLKSPI
1
SPIn
------------
(,
)
=
SPIn
fCLKSPI
fSPCKMAX
MIN fPINMAX
1
SPIn tSETUP
+
------------------------------------
(,
)
=
SPIn
tSETUP
tSETUP fPINMAX
Table 32-42. TWI-Bus Timing Requirements
Symbol
Parameter
Mode
Minimum
Maximum
Unit
Requirement
Device
Requirement
Device
t
r
TWCK and TWD rise time
-
1000
ns
20 + 0.1C
b
300
t
f
TWCK and TWD fall time
Standard
-
300
ns
Fast
20 + 0.1C
b
300
t
HD-STA
(Repeated) START hold time
Standard
4
t
clkpb
-
μs
Fast
0.6
t
SU-STA
(Repeated) START set-up time
Standard
4.7
t
clkpb
-
μs
Fast
0.6
t
SU-STO
STOP set-up time
Standard
4.0
4t
clkpb
-
μs
Fast
0.6
tHD-DAT
Data hold time
Standard
2tclkpb
15tprescaled + tclkpb
μs
Fast