![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_821.png)
821
32099I–01/2012
AT32UC3L016/32/64
atomically. Even if this step is generally described as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
2.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
3.
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
35.4.2
PDCA
1.
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
2.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
3.
VERSION register reads 0x120
The VERSION register reads 0x120 instead of 0x122.
Fix/Workaround
None.
35.4.3
FLASHCDW
1.
Fuse Programming
Programming fuses does not work.
Fix/Workaround
Do not program fuses. All fuses will be erased during chip erase command.
2.
Chip Erase
When performing a chip erase, the device may report that it is protected (IR=0x11) and that
the erase failed, even if it was successful.
Fix/Workaround
Perform a reset before any further read and programming.
3.
Wait 500 ns before reading from the flash after switching read mode
After switching between normal read mode and high-speed read mode, the application must
wait at least 500ns before attempting any access to the flash.