![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_375.png)
375
32099I–01/2012
AT32UC3L016/32/64
Figure 19-16. Receiver Behavior when Operating with Hardware Handshaking
Figure 19-17. Transmitter Behavior when Operating with Hardware Handshaking
Figure 19-18.
19.6.4
SPI Mode
The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting syn-
chronous, full-duplex communication, in both master and slave mode. Writing 0xE (master) or
0xF (slave) to MR.MODE will enable this mode. A SPI in master mode controls the data flow to
and from the other SPI devices, who are in slave mode. It is possible to let devices take turns
being masters (aka multi-master protocol), and one master may shift data simultaneously into
several slaves, but only one slave may respond at a time. A slave is selected when its slave
select (NSS) signal has been raised by the master. The USART can only generate one NSS sig-
nal, and it is possible to use standard I/O lines to address more than one slave.
19.6.4.1
Modes of Operation
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In
master mode this is connected to TXD, and in slave mode to RXD.
Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In
master mode this is connected to RXD, and in slave mode to TXD.
Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both
modes this is connected to CLK.
Slave Select (NSS): This control line allows the master to select or deselect a slave. In
master mode this is connected to RTS, and in slave mode to CTS.
Changing SPI mode after initial configuration has to be followed by a transceiver software reset
in order to avoid unpredictable behavior.
19.6.4.2
Baud Rate
In SPI Master Mode:
RTS
RXBUFF
Write
CR
RXEN = 1
RXD
RXDIS = 1
CTS
TXD