827
32099I–01/2012
AT32UC3L016/32/64
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
3.
VERSION register reads 0x400
The VERSION register reads 0x400 instead of 0x402.
Fix/Workaround
None.
4.
WDT Control Register does not have synchronization feedback
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
35.4.10
FREQM
1.
Measured clock (CLK_MSR) sources 15-17 are shifted
CLKSEL = 14 selects the RC120M AW clock, CLKSEL = 15 selects the RC120M clock, and
CLKSEL = 16 selects the RC32K clock as source for the measured clock (CLK_MSR).
Fix/Workaround
None.
2.
GCLK5 can not be used as source for the CLK_MSR
The frequency for GCLK5 can not be measured by the FREQM.
Fix/Workaround
None.
35.4.11
GPIO
1.
GPIO interrupt can not be cleared when interrupts are disabled
The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin.
Fix/Workaround
Enable interrupt for the corresponding pin, then clear the interrupt.
2.
VERSION register reads 0x210
The VERSION register reads 0x210 instead of 0x211.
Fix/Workaround
None.
35.4.12
USART
1.
The RTS output does not function correctly in hardware handshaking mode