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型號(hào)：	MQ80C52CXXX-25P883R
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	296/849頁(yè)
文件大?。?/td>	12530K
代理商：	MQ80C52CXXX-25P883R

32099I–01/2012

AT32UC3L016/32/64

Functional Description

Baud Rate Generator

The baud rate generator provides the bit period clock named the Baud Rate Clock to both

receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider

field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,

and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode

CLK_USART (internal clock)

CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)

CLK (external clock, available on the CLK pin)

If the external CLK clock is selected, the duration of the low and high levels of the signal pro-

vided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.

Figure 19-2. Baud Rate Generator

Baud Rate in Asynchronous Mode

If the USART is configured to operate in an asynchronous mode, the selected clock is divided by

the CD value before it is provided to the receiver as a sampling clock. Depending on the Over-

sampling Mode bit (MR.OVER) value, the clock is then divided by either 8 (OVER=1), or 16

(OVER=0). The baud rate is calculated with the following formula:

This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is

the fastest clock possible, and that OVER is one.

Baud Rate Calculation Example

Table 19-3 shows calculations based on the CD field to obtain 38400 baud from different source

clock frequencies. This table also shows the actual resulting baud rate and error.

16-bit Counter

CLK_USART/DIV

SelectedClock

------------------------------------------------

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