1062
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The dith-
ering pattern for the first pair member is the inversion of the one for the second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)th bit of the pattern determines if a pixel with horizon-
tal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame.
The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. The
four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is DP3_5 =”1010 0101 1010
0101 1111”.
The output sequence obtained in the data output for monochrome mode is shown in
Table 45-12.Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. A
color pixel is composed of three components: {R, G, B}. Pixel p0 will be displayed sending the color components
{R0, G0, B0} to the display. Pixel p1 will be displayed sending the color components {R1, G1, B1}. Suppose that
11
5/7
DP5_7
10
2/3
DP2_3
9
3/5
DP3_5
8
4/7
DP4_7
7
1/2
~DP1_2
6
3/7
~DP4_7
5
2/5
~DP3_5
4
1/3
~DP2_3
3
1/4
~DP3_4
2
1/5
~DP4_5
1
1/7
~DP6_7
00-
Table 45-12. Dithering Algorithm for Monochrome Mode
Frame
Number
Pattern
Pixel a
Pixel bPixel c
Pixel d
N
1010
ON
OFF
ON
OFF
N+1
0101
OFF
ON
OFF
ON
N+2
1010
ON
OFF
ON
OFF
N+3
0101
OFF
ON
OFF
ON
N+4
1111
ON
N+5
1010
ON
OFF
ON
OFF
N+6
0101
OFF
ON
OFF
ON
N+7
1010
ON
OFF
ON
OFF
...
Table 45-11. Dithering Duty Cycle (Continued)
Gray Level
Duty Cycle
Pattern Register