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型號(hào)：	MQ80C32-20
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 20 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁數(shù)：	334/1185頁
文件大?。?/td>	5451K
代理商：	MQ80C32-20

SAM9G45 [DATASHEET]

6438K–ATARM–12-Feb-13

13. Program DLL field into the Configuration Register (see Section 22.8.3 on page 256) to low (Disable DLL

14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices, in

particular CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the

Mode Register (see Section 22.8.1 on page 254) and perform a write access to the DDR2-SDRAM to

acknowledge this command. The write address must be chosen so that BA[1:0] are set to 0. For example,

with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access

should be done at the address 0x20000000

15. Program OCD field into the Configuration Register (see Section 22.8.3 on page 256) to high (OCD cali-

bration default).

16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The application must set

Mode to 5 in the Mode Register (see Section 22.8.1 on page 254) and perform a write access to the

DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0

and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks)

bank address, the DDR2-SDRAM write access should be done at the address 0x20400000.

17. Program OCD field into the Configuration Register (see Section 22.8.3 on page 256) to low (OCD calibra-

tion mode exit).

18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must set

Mode to 5 in the Mode Register (see Section 22.8.1 on page 254) and perform a write access to the

DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0

and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks)

bank address, the DDR2-SDRAM write access should be done at the address 0x20400000.

19. A mode Normal command is provided. Program the Normal mode into Mode Register (see Section 22.8.1

on page 254). Perform a write access to any DDR2-SDRAM address to acknowledge this command.

20. Perform a write access to any DDR2-SDRAM address.

21. Write the refresh rate into the count field in the Refresh Timer register (see page 255). (Refresh rate =

delay between refresh cycles). The DDR2-SDRAM device requires a refresh every 15.625 μs or 7.81 μs.

With a 133 MHz frequency, the refresh timer count register must to be set with (15.625*133 MHz) = 2079

i.e. 0x081f or (7.81*133 MHz) = 1039 i.e. 0x040f.

After initialization, the DDR2-SDRAM devices are fully functional.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MQ82370-20	制造商:Rochester Electronics LLC 功能描述:- Bulk
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MQ82380-20	制造商:Rochester Electronics LLC 功能描述:- Bulk
MQ82380-20/R	制造商:Rochester Electronics LLC 功能描述:
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