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SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
Doc. Rev
6438F
Comments
Change
Request
Ref.
Bus Matrix
- EBI_DRIVE and DDR_DRIVE bitfields edited in “EBI Chip Select Assignment Register”
- “12-layer” Matrix instead of “11-layer”
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DDRSDRC
In Section 22.8.6 “DDRSDRC Timing Parameter 2 Register”,
- TRTP bitfield reset value (0 --> 2) changed.
- 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP: Read to Precharge”.
- TXARD (-->2), TXARDS (-->6), and TRPA (-->0) reset values changed.
In Section 22.8.7 “DDRSDRC Low-power Register”, UPD_MR bitfield added to the table at [21:20].
In Section 22.5.4.1 “Self Refresh Mode”, UDP_EN bitfield replaced by UPD_MR.
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Electrical Characteristics
- Figure below Table 46-7, “Main Oscillator Characteristics” edited.
- Section 46.14 “DDRSDRC Timings” updated.
- Table 46-17 “I/O Characteristics” and Notes below edited.
- Ultra low power Mode value changed in Table 46-3, “Power Consumption for Different Modes”.
- Section 46.15.1.1 “Maximum SPI Frequency” added.
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Errata
- “Boot ROM” errata added.
- “Static Memory Controller (SMC)” errata added.
- “Touch Screen (TSADCC)” errata added.
- “USB High Speed Host Port (UHPHS)” errata added.
- 3 “Error Corrected Code Controller (ECC)” errata added: “ECC: Uncomplete parity status when error in
ECC parity” , “ECC: Unsupported ECC per 512 words” and “ECC: Unsupported hardware ECC on 16-bit
Nand Flash”
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External Memories
- DQM0-3 added to Figure 20-4 “EBI Connections to Memory Devices”.
- Table 20-5, row ‘A15’ edited.
- Section 20.2.7.7 “NAND Flash Support” edited.
- Section 20. “External Memories” reorganized.
- On Figure 6-1 “SAM9G45 Memory Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and ‘DDR2-
LPDDR’ --> ‘DDRSDRC20’.
- All ‘DDR2SDRC’ changed into ‘DDRSDRC’.
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Mechanical Characteristics
- New Figure 47-1 “324-ball TFBGA Package Drawing” and Max. weight changed in Table 47-2
- All ‘nominal’ changed into ‘typical’.
- An empty square after letter ‘V’ removed from the Section 49.1 “SAM9G45 Errata - Rev. A Parts” table.
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RFO
PMC
- Note added to Section 26.4 “Master Clock Controller” and Section 26.12.12 “PMC Master Clock
Register”.
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USART
- LIN Mode condition now shown in Section 33. “Universal Synchronous Asynchronous Receiver
Transmitter (USART)”.
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