參數(shù)資料
型號: MPC7400RX300LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 43/44頁
文件大?。?/td> 504K
代理商: MPC7400RX300LX
8
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
4. Caution: Vdd/AVdd/L2AVdd must not exceed L2OVdd/OVdd by more than 0.4V at any time including during power-on
reset. In addition, operation at nominal Vdd/AVdd/L2AVdd greater than nominal L2OVdd or OVdd in the 1.8V input
threshold select mode can cause erratic operation and AC timing values worse than described in this specication.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Figure 2 shows the undershoot and overshoot voltage on the MPC7400.
Figure 2. Overshoot/Undershoot Voltage
The MPC7400 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7400 “core” voltage must always be provided at nominal 1.8V (see
Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied
to the OVdd or L2OVdd power pins.
Table 2. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input
Threshold is Relative to:
L2VSEL Signal
L2 Bus Input Threshold is
Relative to:
Note
0
1.8V
0
1.8
1
HRESET
2.5V
HRESET
2.5
1,2
1
3.3V
1
3.3
1
Notes:
1. Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied.
2. To select the 2.5 volt threshold option, L2VSEL / BVSEL should be tied to HRESET so that the two signals
change state together.
VIH
Gnd
Gnd - .3V
Gnd - 0.7V
Not to exceed 10%
(L2)OVdd + 20%
VIL
(L2)OVdd
(L2)OVdd + 5%
of tSYSCLK
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