- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45352 > MPC7400RX300LX (MOTOROLA INC) 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 PDF資料下載
參數(shù)資料
| 型號： | MPC7400RX300LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 14/44頁 |
| 文件大小： | 504K |
| 代理商： | MPC7400RX300LX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
MPC7400 RISC Microprocessor Hardware Specications
21
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC7400.
Figure 8. L2 Bus Input Timing Diagrams
Valid Times:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOV
-
2.5
3.0
3.5
4.0
ns
3,4
Output Hold Times
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOX
0.4
1.0
1.4
1.8
-
ns
3
L2SYNC_IN to high impedance:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOZ
-
2.0
2.5
3.0
3.5
ns
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVdd.
2. All input specications are measured from the midpoint of the signal in question to the
midpoint voltage of the rising edge of the input L2SYNC_IN (see Figure 8). Input timings
are measured at the pins.
3. All output specications are measured from the midpoint voltage of the rising edge of
L2SYNC_IN to the midpoint of the signal in question. The output timings are measured at
the pins. All output timings assume a purely resistive 50 ohm load (See Figure 10).
4.The outputs are valid for both single-ended and differential L2CLK modes. For pipelined
registered synchronous burst RAMs, L2CR[14–15] = 00 is recommended. For pipelined
late-write synchronous burst SRAMs, L2CR[14–15] = 10 is recommended.
Table 11. L2 Bus Interface AC Timing Specifications (Continued)
At Vdd=AVdd=L2AVdd=1.8V±100mV; 0 ≤ Tj ≤ 105°C, L2OVdd = 3.3V±165mV or L2OVdd = 2.5V±100mV or L2OVdd=1.8V±100mV
Parameter
Symbol
350, 400 MHz
Unit
Notes
Min
Max
L2SYNC_IN
L2 DATA AND DATA
VM
VM = Midpoint Voltage (L2OVDD/2)
tDVL2CH
tDXL2CH
tL2CR
tL2CF
PARITY INPUTS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC7400RX333TX | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360 |
| MPC7400RX400LX | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| MPC7400RX400TX | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| MPC740ARX233LX | 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255 |
| MPC740ARX200LX | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC7410 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC7410_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7410_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC74-103J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC74-103K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。