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參數(shù)資料
| 型號： | MPC7400RX300LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大小： | 504K |
| 代理商： | MPC7400RX300LX |
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20
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap
back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and
the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects
L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and
does not have to be considered in the L2 timing analysis.
The L2CLK_OUT timing diagram is shown in Figure 7.
Figure 7. L2CLK_OUT Output Timing Diagram
1.4.2.4 L2 Bus AC Specications
Table 11 provides the L2 bus interface AC timing specications for the MPC7400 as dened in Figure 8 and
Figure 9 for the loading conditions described in Figure 10.
Table 11. L2 Bus Interface AC Timing Specifications
At Vdd=AVdd=L2AVdd=1.8V±100mV; 0 ≤ Tj ≤ 105°C, L2OVdd = 3.3V±165mV or L2OVdd = 2.5V±100mV or L2OVdd=1.8V±100mV
Parameter
Symbol
350, 400 MHz
Unit
Notes
Min
Max
L2SYNC_IN rise and fall time
tL2CR & tL2CF
—
1.0
ns
1
Setup Times:
Data and parity tDVL2CH
1.5
—
ns
2
Input Hold Times:
Data and parity tDXL2CH
0.0
—
ns
2
VM = Midpoint Voltage (L2OVdd/2)
L2CLK_OUTA
L2CLK_OUTB
L2 Differential Clock Mode
L2 Single-Ended Clock Mode
L2SYNC_OUT
tL2CLK
tCHCL
L2CLK_OUTA
VM
tL2CR
tL2CF
VM
L2CLK_OUTB
VM
tL2CLK
tCHCL
L2SYNC_OUT
VM
tL2CSKW
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