參數(shù)資料
型號(hào)： MPC7400RX300LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 40/44頁(yè)
文件大小： 504K
代理商： MPC7400RX300LX
MPC7400 RISC Microprocessor Hardware Specications
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
AltiVec Unit
— Full 128-bit data paths
— Two dispatchable units: vector permute unit and vector ALU unit.
— Contains its own 32-entry 128-bit vector register le (VRF) with 6 renames
— The vector ALU unit is further sub-divided into the vector simple integer unit (VSIU), the
vector complex integer unit (VCIU), and the vector oating-point unit (VFPU).
— Fully pipelined
Load/store unit
— One cycle load or store cache access (byte, half word, word, double-word)
— 2 cycle load latency with 1 cycle throughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register le
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store trafc
— Complete support for all 4 architecture AltiVec DST streams
Level 1 (L1) cache structure
— 32K, 32-byte line, 8-way set associative instruction cache (iL1)
— 32K, 32-byte line, 8-way set associative data cache (dL1)
— Single-cycle cache access
— Pseudo least-recently-used (LRU) replacement
— Data cache supports AltiVec LRU and transient instructions algorithm
— Copy-back or write-through data cache (on a page per page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking instruction and data cache
— Separate copy of data cache tags for efcient snooping
— No snooping of instruction cache except for ICBI instruction
Level 2 (L2) cache interface
— Internal L2 cache controller and tags; external data SRAMs
— 512K, 1M, and 2Mbyte 2-way set associative L2 cache support
— Copyback or write-through data cache (on a page basis, or for all L2)
— 32 byte (512K), 64 byte (1M), or 128 byte (2M) sectored line size
— Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-
register) late-write synchronous burst SRAMs
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64 bit data bus
— Selectable interface voltages of 1.8, 2.5, and 3.3V.
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