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參數(shù)資料
| 型號(hào)： | MPC7400RX300LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 30/44頁 |
| 文件大?。?/td> | 504K |
| 代理商： | MPC7400RX300LX |
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36
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
HRESET or TRST in order to fully control the processor. If the target system has independent reset sources,
such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP
reset signals must be merged into these signals with logic.
The arrangement shown in Figure 21 allows the COP to independently assert HRESET or TRST, while
insuring that the target can drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG
scan chain is initialized during power-on if a JTAG interface cable is not attached; if it is, it is responsible
for driving TRST when needed.
Figure 21. Suggested TRST connection
The COP header shown in Figure 21 adds many benets—breakpoints, watchpoints, register and memory
examination/modication and other standard debugger features are possible through this interface – and can
be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025" square-
post 0.100" centered header assembly (often called a “Berg” header). The connector typically has pin 14
removed as a connector key, as shown in Figure 22.
Figure 22. COP Connector Diagram
MPC7400
HRESET
TRST
From Target
Board
Sources
COP Header
2K
QACK
2K
3
CKSTP_OUT
13
9
5
1
6
10
2
TOP VIEW
15
11
7
16
12
8
4
KEY
No pin
HRESET
SRESET
TMS
RUN/ST
OP
TCK
TDI
TDO
Ground
TRST
VDD_SENSE
Pins 10, 12 and 14 are no-connects.
Pin 14 is not physically present
QACK
CHKSTP_IN
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