參數(shù)資料
型號(hào)： MPC7400RX300LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 11/44頁(yè)
文件大?。?/td> 504K
代理商： MPC7400RX300LX
MPC7400 RISC Microprocessor Hardware Specications
19
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
The minimum L2CLK frequency of Table 10 is specied by the maximum delay of the internal DLL. The
variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB, and
L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock
(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below
this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the
MPC7400 core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 10 is the core frequency divided by one. Very few L2
SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to
provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK
frequency for any application of the MPC7400 will be a function of the AC timings of the MPC7400, the
AC timings for the SRAM, bus loading, and printed circuit board trace length.
Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a
socketed part on a functional tester at the maximum frequencies of Table 10. Therefore functional operation
and AC timing information are tested at core-to-L2 divisors of 2 or greater.
L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC
timings of Table 11 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN
is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of
L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since in
a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Table
11 are referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing
test, these times are actually measured relative to SYSCLK.
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core frequency
settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective
maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent..
L2CLK_OUTA and L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re-lock time is specied in terms of L2CLKs. The number in the table must be multiplied by the period of
L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the
DLL.
Table 10. L2CLK Output AC Timing Specifications
At recommended operating conditions (See Table 3)
Parameter
Symbol
350 MHz
400 MHz
Unit
Notes
Min
Max
Min
Max
L2CLK frequency
fL2CLK
100
350
133
400
MHz
1,4
L2CLK cycle time
tL2CLK
2.86
10
2.5
7.5
ns
L2CLK duty cycle
tCHCL/tL2CLK
50
%
2
Internal DLL-relock time
640
—
640
—
L2CLK
3
DLL capture window
0
10
0
10
ns
5
L2CLKOUT output-to-
output skew
tL2CSKW
50
ps
6
L2CLKOUT output jitter
±150
ps
6
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