參數(shù)資料
型號: MPC5554AVR132R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PBGA416
封裝: 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, TEPBGA-416
文件頁數(shù): 52/58頁
文件大?。?/td> 1452K
代理商: MPC5554AVR132R2
MPC5554 Microcontroller Data Sheet, Rev. 2.0
Revision History for the MPC5554 Data Sheet
Freescale Semiconductor
56
Rev. 2.0
Table 12 FMPLL Electrical Characteristics:
Added (TA = TL – TH) to the second line of the table title.
Old footnote 2: ‘Nominal crystal and external reference values are worst-case not more than
1%. The device operates correctly if the frequency remains within ± 5% of the specification
limit. This tolerance range allows for a slight frequency drift of the crystals over time. The
designer must thoroughly understand the drift margin of the source clock.‘ was moved
to the end of 1st row in column 2: ‘PLL reference frequency range.’ moving the footnote
location changed it to footnote 1. Deleted old footnote 2 from all Min and Max columns.
Deleted old footnote 18 from row 21, from the MAX column that reads:
The ICO frequency can be higher than the maximum allowable system frequency. For this
case, set the CMPLL synthesizer control register reduced frequency divider
(FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001). Therefore, for a 40 MHz maximum
device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and
then divide-by-two the RFD to provide the 40 MHz system clock.’
Table 13 eQADC Conversion Specifications: Added (TA = TL – TH) to the table title.
Table 14 Flash Program and Erase Specifications:
Added (TA = TL – TH) to the table title.
Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
Footnote 2: Changed from: ‘Initial factory condition:
≤ 100 program/erase cycles, 25 oC, typical
supply voltage, 80 MHz minimum system frequency.‘ To: ‘Initial factory condition:
≤ 100
program/erase cycles, 25 oC, using a typical supply voltage measured at a minimum system
frequency of 80 MHz.’
Table 15 Flash EEPROM Module Life Specifications: Replaced (Full Temperature Range) with
(TA = TL – TH) in the table title.
Table 16 Flash BIU Settings vs. Frequency of Operation:
Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist.
Use entries from the same row in this table.’
Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column
header.
Deleted the x-refs in the ‘DPFEN’ column for the rows.
Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
Deleted the x-refs in the ‘IPFEN’ column for the rows.
Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column
header.
Deleted the x-refs in the ‘PFLIM’ column for the rows.
Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
Deleted the x-refs in the ‘BFEN’ column for the rows.
Table 27 eQADC SSI Timing Characteristics:
Deleted first header row that reads ‘CLOAD = 25 pF on all outputs. Pad drive strength set to
maximum.’
Deleted from footnote 1: ‘FSYS = 132 MHz, VDD = 1.35–1.65 V, VDD33 and VDDSYN = 3.0–3.6
V.’ and changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
9/20/07
Table 28. MPC5554 Revision History (continued)
Revision
Substantive Change(s)
Date
相關(guān)PDF資料
PDF描述
MPC5554MZP80R2 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PBGA416
MPC5554AVR132 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416
MPC5554MVR112 32-BIT, FLASH, 112 MHz, MICROCONTROLLER, PBGA416
MPC5554MZP132R2 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416
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