參數(shù)資料
型號(hào)： MPC5554AVR132R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PBGA416
封裝： 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, TEPBGA-416
文件頁(yè)數(shù)： 4/58頁(yè)
文件大?。?/td> 1452K
代理商： MPC5554AVR132R2
MPC5554 Microcontroller Data Sheet, Rev. 2.0
Electrical Characteristics
Freescale Semiconductor
12
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time
required to enable the external circuitry connected to the device outputs.
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
Figure 2. Power-Up Sequence (VRC33 Grounded)
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence when VRC33 is grounded is that if VDD decreases to
less than its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the
VDD power is allowed to increase to its operating range. This ensures that the digital 1.5 V logic, which is
reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset
properly.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
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