參數(shù)資料
型號: MPC5554AVR132R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PBGA416
封裝: 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, TEPBGA-416
文件頁數(shù): 33/58頁
文件大?。?/td> 1452K
代理商: MPC5554AVR132R2
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
39
9
Data setup time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
tSUI
20
2
–4
20
20
2
3
20
20
2
6
20
ns
10
Data hold time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
tHI
–4
7
21
–4
–4
7
14
–4
–4
7
12
–4
ns
11
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
5
25
18
5
5
25
14
5
5
25
13
5
ns
12
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
–5
5.5
8
–5
–5
5.5
4
–5
–5
5.5
3
–5
ns
1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of
S or SH have an additional delay based on the slew rate. DSPI timing is specified at: VDDEH = 3.0–5.5 V;TA = TL to TH;
and CL = 50 pF with SRC = 0b11.
2 The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
3 The actual minimum SCK cycle time is limited by pad performance.
4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
6 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
Table 26. DSPI Timing1 (continued)
Spec
Characteristic
Symbol
80 MHz
112 MHz
132 MHz
Unit
Min
Max
Min
Max
Min
Max
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