參數(shù)資料
型號(hào): MPC5554AVR132R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PBGA416
封裝: 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, TEPBGA-416
文件頁(yè)數(shù): 32/58頁(yè)
文件大?。?/td> 1452K
代理商: MPC5554AVR132R2
MPC5554 Microcontroller Data Sheet, Rev. 2.0
Electrical Characteristics
Freescale Semiconductor
38
3.13.7
eMIOS Timing
Figure 17. eMIOS Timing
3.13.8
DSPI Timing
Table 25. eMIOS Timing1
1 eMIOS timing specified at: V
DDEH = 3.0–5.5 V; and TA = TL to TH.
Spec
Characteristic
Symbol
Min
Max
Unit
1
eMIOS input pulse width
tMIPW
4—
tCYC
2
eMIOS output pulse width
tMOPW
12
2 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
—tCYC
Table 26. DSPI Timing1
Spec
Characteristic
Symbol
80 MHz
112 MHz
132 MHz
Unit
Min
Max
Min
Max
Min
Max
1
SCK cycle time2, 3
tSCK
25 ns
2.9 ms
17.9 ns
2.0 ms
15.2 ns
1.7 ms
2
PCS to SCK delay4
tCSC
23
15
13
ns
3
After SCK delay5
tASC
22
14
12
ns
4
SCK duty cycle
tSDC
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2)
+ 2 ns
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2)
+ 2 ns
(tSCK ÷ 2)
– 2 ns
(tSCK ÷ 2)
+ 2 ns
ns
5
Slave access time
(SS active to SOUT driven)
tA
25
25
25
ns
6
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
tDIS
25
25
25
ns
7PCSx to PCSS time
tPCSC
4—
4
4
ns
8PCSS to PCSx time
tPASC
5—
5
5
ns
1
2
eMIOS
output
eMIOS input
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