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| 型號： | MPC5554AVR132R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PBGA416 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, TEPBGA-416 |
| 文件頁數(shù)： | 48/58頁 |
| 文件大?。?/td> | 1452K |
| 代理商： | MPC5554AVR132R2 |
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MPC5554 Microcontroller Data Sheet, Rev. 2.0
Revision History for the MPC5554 Data Sheet
Freescale Semiconductor
52
Rev. 2.0
Table 7 Power Sequence Pin Status for the Fast Pad: Changed preceding paragraph
From: Although there are no power up/down sequencing requirements to prevent issues like
latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down
varies depending on power. Prior to exiting POR, the pads are in a high impedance state
(Hi-Z).
To: There are no power up/down sequencing requirements to prevent issues such as latch-up,
excessive current spikes, and so on. Therefore, the state of the I/O pins during power
up/down varies depending on which supplies are powered.
From: To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG
are not treated as ones (1s) when POR negates, VDD33 must not lag VDDSYN and the
RESET pin power (VDDEH6) when powering the device by more than the VDD33 lag
specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET power
pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the
VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag
specification. This VDD33 lag specification only applies during power up. VDD33 has no
lead or lag requirements when powering down.
To:
When powering the device, VDD33 must not lag VDDSYN and the RESET power pin
(VDDEH6) by more than the VDD33 lag specification listed in Table 6. This avoids
accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1]
and RSTCFG are not powered and therefore cannot read the default state when POR
negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both
by more than the VDD33 lag specification. This VDD33 lag specification only applies during
power up. VDD33 has no lead or lag requirements when powering down.
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)” Deleted the underscore in
ORed_POR to become ORed POR.
Table 22 Bus Operation Timing: Specs 7 and 8: Added the following signals to Specs 7 and 8 the
EBI section: OE, RD_WR, TEA, BDIP, BG, BR, BB, and TSIZ[0:1].
02/07/07
Rev. 2.0
Table 6 VCR/POR Electrical Specifications – Added to Spec 2:
3.3 V (VDDSYN) POR negated (ramp down)
Min 0.0
Max 0.30
V
3.3 V (VDDSYN) POR asserted (ramp up)
Min 0.0
Max 0.30 V
3/12/07
Rev. 2.0
Page 2 and throughout: Replaced kilobytes with KB and megabytes with MB.
Table 1 Orderable Part Numbers: Changed the maximum operating speed from 132 MHz
to 135 MHz.
Table 6 VCR/POR Electrical Specifications: Changed the order of the entries in spec 2 from:
3.3 V (VDDSYN) POR negated (ramp down)
0.0
0.30 V
3.3 V (VDDSYN) POR negated (ramp up)
2.0
2.85 V
3.3 V (VDDSYN) POR asserted (ramp down)
2.0
2.85 V
3.3 V (VDDSYN) POR asserted (ramp up)
0.0
0.30 V
to:
3.3 V (VDDSYN) POR asserted (ramp up)
0.0
0.30 V
3.3 V (VDDSYN) POR negated (ramp up)
2.0
2.85 V
3.3 V (VDDSYN) POR asserted (ramp down)
2.0
2.85 V
3.3 V (VDDSYN) POR negated (ramp down) 0.0
0.30 V
Table 12 FMPLL Electrical Characteristics: Added footnote to Spec 1 on the minimum and
maximum values for: Crystal reference, External reference, and Dual controller entries. The
footnote reads:
‘The device operates correctly if the frequency remains within ± 5% of the specification limit. This
tolerance range allows for a slight frequency drift of the crystals over time. The designer must
thoroughly understand the drift margin of the source clock.’
3/19/07
Table 28. MPC5554 Revision History (continued)
Revision
Substantive Change(s)
Date
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC5554MZP80R2 | 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PBGA416 |
| MPC5554AVR132 | 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416 |
| MPC5554MVR112 | 32-BIT, FLASH, 112 MHz, MICROCONTROLLER, PBGA416 |
| MPC5554MZP132R2 | 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416 |
| MPC555LFCZP40 | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA272 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5554AZP132 | 功能描述:32位微控制器 - MCU MPC5554 COPPERHEAD RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MPC5554EVB | 功能描述:開發(fā)板和工具包 - 其他處理器 MPC5554 CUSTOMER Qorivva RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC5554EVBE | 功能描述:開發(fā)板和工具包 - 其他處理器 MPC5554 CUSTOMER Qorivva RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC5554EVBE | 制造商:Freescale Semiconductor 功能描述:MPC5554 CUSTOMER DEMO BD |
| MPC5554EVBGHS | 功能描述:開發(fā)軟件 GREEN HILLS SW Qorivva RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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