參數(shù)資料
型號： ML87V3116
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： DOT MAT LCD DSPL CTLR, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù)： 9/46頁
文件大?。?/td> 273K
代理商： ML87V3116
PEDL87V3116-02
OKI Semiconductor
ML87V3116
17/47
2.2.4 Display Data Area Partition, Display/Hide
The effective data area of the display output can be divided into four partitions. Horizontal division or vertical
division can be selected, and the data buffer address of data to be displayed in each of the four areas can be
specified individually.
Also, the specified area can be hidden. Hidden areas are not used to read the data buffers.
[Control Registers]
DASMOD
: Display area partition mode, 1 bit (write/read)
“0”: Horizontal partition, “1”: Vertical partition
DIVAP1
: Display area 0-1 partition point, 10 bits (write/read)
DIVAP2
: Display area 1-2 partition point, 10 bits (write/read)
DIVAP3
: Display area 2-3 partition point, 10 bits (write/read)
DA0SAX
: Data buffer read start X address for display area 0, 8-pixel units
12 bits (write/read)
DA0SAY
: Data buffer read start Y address for display area 0, 8-line units
12 bits (write/read)
DA1SAX
: Data buffer read start X address for display area 1, 8-pixel units
12 bits (write/read)
DA1SAY
: Data buffer read start Y address for display area 1, 8-line units
12 bits (write/read)
DA2SAX
: Data buffer read start X address for display area 2, 8-pixel units
12 bits (write/read)
DA2SAY
: Data buffer read start Y address for display area 2, 8-line units
12 bits (write/read)
DA3SAX
: Data buffer read start X address for display area 3, 8-pixel units
12 bits (write/read)
DA3SAY
: Data buffer read start Y address for display area 3, 8-line units
12 bits (write/read)
DPENB0-3
: Partition area display enable, 4 bits (write/read)
“0”: Display, “1”: Hide (each bit)
BLKCOL
: Output data in hidden area, 1 bit (write/read)
“0”: All “L”, “1”: All “H”
DOPSNG
: Positive/negative mode of output data, 4 bits (write/read)
“0”: Normal mode (positive), “1”: All bits reversed (negative)
DISP
: DISP signal output level, 1 bit (write/read)
“0”: “L” level, “1”: “H” level
相關(guān)PDF資料
PDF描述
ML9041-XXACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9041-01BCVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175
ML9041A-XXACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9042-XXCVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
ML9044-XXACVWA 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
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