參數(shù)資料
型號(hào): ML87V3116
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 顯示控制器
英文描述: DOT MAT LCD DSPL CTLR, PQFP176
封裝: 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁數(shù): 31/46頁
文件大小: 273K
代理商: ML87V3116
PEDL87V3116-02
OKI Semiconductor
ML87V3116
37/47
2.7 Clock/Power Manager
2.7.1 General Description
The system clock of the ML87V3116 uses the same pixel clock frequency as display output or a frequency of
x2, x4 or x8. This clock generates the REFCLK input by a built-in PLL using simple integer ratio n/m (n and m
are 1 to 255) as a reference. Power saving can be achieved by setting to a slower system clock frequency at
standby.
The video input clock VCLK and host interface bus clock BCLK are asynchronous with the system clock. The
frequency ratio to the system clock can be set in a range of 1:10 to 10:1.
The system clock is distributed to each function block and its ON/OFF can be controlled individually.
The types of a clock to be distributed are:
Video input interface
Display output interface
JPEG Codec
Rectangle copy controller
Data buffer controller and internal SDRAM
External SDRAM clock for extension data buffers
I2C bus master
Synchronous serial interface (SPI) master
SD card controller
Memory stick controller
相關(guān)PDF資料
PDF描述
ML9041-XXACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9041-01BCVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175
ML9041A-XXACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9042-XXCVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
ML9044-XXACVWA 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
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