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| 型號： | ML87V3116 |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | DOT MAT LCD DSPL CTLR, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 46/46頁 |
| 文件大?。?/td> | 273K |
| 代理商： | ML87V3116 |
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PEDL87V3116-02
OKI Semiconductor
ML87V3116
9/47
2. Function of Each Block
2.1 Video Input Interface
2.1.1 Video Input Ports
There are three types of video input formats.
BT.656 format
: An 8-bit format defined in ITU-R Rec. BT.656
8-bit format
: A format that deletes the synchronous reference code (EAV/SAV) from BT.656 format,
and inputs the horizontal synchronous signal, vertical synchronous signal and field ID
separately
16-bit format
: A format that inputs 8 bits of brightness Y data, 8 bits of color difference C data into
which Cb/Cr data are multiplexed, horizontal synchronous signal, vertical synchronous
signal and field ID
Either one of two inputs, Y port (VY7-0) and C port (VC7-0), can be selected in BT.656 format.
8-bit format data uses only the Y port.
[Control Registers]
VMDSEL
: Input video format selection, 2 bits (write/read)
“00”: BT.656 format/ “01”: 8-bit format/ “10”: 16-bit format
VPTSEL
: Port selection in BT.656 mode, 1 bit (write/read)
2.1.2 Synchronous Signal Format for Video Input
Synchronous signals of video input include the horizontal synchronous signal (VHS), vertical synchronous
signal (VVS), field ID signal (FID) and data clock (VCLK). A pulse polarity can be selected for each of the
synchronous signals.
The FID signal can be used only at the time of interlace input. When the FID input does not operate, whether
the input is an interlace input or a progressive input is automatically determined based on the pulse phase
relationship between the VHS signal and the VVS signal. In the case of interlace input, an internal field ID
signal is generated.
When VHS or VVS signal does not operate, it is determined as an ITU-R Rec. BT.656 input. Then, an internal
horizontal synchronous signal and vertical synchronous signal are generated from the synchronous reference
code (EAV/SAV) included in the data.
ITU-R BT.656 format is based on the video data interface standard for TV format. However, if data is within
the designated data range and uses the synchronous reference code (EAV/SAV), it can be input as a signal that
conforms to the standard even if the image size is different.
[Control Registers]
HSPOL
: Horizontal synchronous signal polarity, 1 bit (write/read)
VSPOL
: Vertical synchronous signal polarity, 1 bit (write/read)
FIDPOL
: Field ID polarity, 1 bit (write/read)
HSCYC
: Horizontal synchronous signal cycle, 12 bits (read only)
VSCYC
: Vertical synchronous signal cycle, 12 bits (read only)
HVDET
: VHS signal, VVS signal detection, 1 bit (read only)
IPDET
: Interlace/progressive detection, 1 bit (read only)
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