參數(shù)資料
型號(hào)： ML60851AGA
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù)： 8/45頁
文件大?。?/td> 358K
代理商： ML60851AGA
ML60851A
Semiconductor
16/44
Endpoint 3 Control Register (F8h, 78h)
Register to set the attribute of EP3.
To use EP3, the local MCU writes EP3's attribute in this register by the request from the host
computer.
Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer
to this EP is received. The packet is ignored when this bit is deasserted ("0").
Whether or not this EP is configured can be known by referencing this bit.
Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host
computer to this EP is automatically returned to the host computer.
Toggle Condition Bit: When this bit is "0", DATA0 and DATA1 are toggled each time ACK is
received form the host computer by the EP3. Setting this bit to "1" causes the ML60851A to go
into the rate feedback mode, in which case DATA0 and DATA1 are toggled each time the packet
ready is asserted by the local MCU.
Endpoint 3 General Register (F9h, 79h)
Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data
Packet Toggle bit by writing "1" to this bit (this bit goes to "0").
Endpoint 3 Payload Register (FAh, 7Ah)
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Bit (R/W)
01
111
11 = Interrupt Transfer
Endpoint Address (R)
Stall Bit (R/W)
Transfer Type (R)
0 = Number
1 = Rate Feedback Mode
Toggle Condition (R/W)
RFU
D7
D6
D5
D4
D3
D2
D1
D0
Data Sequence
Toggle Bit (R/Reset)
Maximum packet size (R/W)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
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