參數(shù)資料
型號: ML60851AGA
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù): 43/45頁
文件大?。?/td> 358K
代理商: ML60851AGA
ML60851A
Semiconductor
7/44
Register Description
Device Address Register (C0h, 40h)
RFU
D7
D6
D5
D4
D3
D2
D1
D0
Device Address (R/W)
The local MCU writes a device address, which is given by the SET_ADDRESS command form the
host computer, into this register. Thereafter, this device processes an only token packet transmitted
to the given device address.
Device State Register (C1h, 41h)
RFU
D7
D6
D5
D4
D3
D2
D1
D0
Default State (R/W)
Address State (R/W)
Configuration State (R/W)
Suspended State (R)
USB Bus Reset Clear (W)
Remote Wakeup (R/W)
Default, Address, and Configuration States: D2, D1, and D0 are set to 0, 0, and 1 (default states) by
reset respectively. Changing the values of this register gives no influence on operation of this
device.
Suspended State: This register is asserted when the device enters the suspended state.
This register is deaserted by reset or when the device exits the suspended state by a resume signaling
from the USB bus.
Remote Wakeup: When this device signals a remote wakeup during the suspended state, this
register is asserted by a local MCU. This register is automatically deasserted when the device exits
the suspended state by a resume signaling from the USB bus.
USB Bus Reset Status Clear: Writing "1" to this bit causes the interrupt status to be cleared (the USB
bus reset interrupt status bit is "0" and the INTR pin is deasserted) while the USB bus reset interrupt
is being serviced (when D5, the USB bus reset interrupt status bit, of the interrupt status register is
"1" and the INTR pin is asserted). This bit is readable, and when read, its value will be always "0".
Packet Error Register (C2h, –)
RFU
D7
D6
D5
D4
D3
D2
D1
D0
Bit Stuff Error (R)
Data CRC Error (R)
Address CRC Error (R)
PID Error (R)
RFU = 0000b
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