參數(shù)資料
型號(hào)： ML60851AGA
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù)： 10/45頁(yè)
文件大小： 358K
代理商： ML60851AGA
ML60851A
Semiconductor
18/44
Endpoint 2 Control Register (F4h, 74h)
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Bit (R/W)
01
010
10 = Bulk Transfer
Endpoint Address (R)
Stall Bit (R/W)
Transfer Type (R)
0 = Reception (OUT endpoint)
1 = Transmission (IN endpoint)
Transfer Direction (R/W)
Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer
to this EP is received. The packet is ignored when this bit is deasserted ("0").
Whether or not this EP is configured can be known by referencing this bit.
Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host
computer to this EP is automatically returned to the host computer.
Endpoint 2 General Register (F5h, 75h)
RFU
D7
D6
D5
D4
D3
D2
D1
D0
Data Sequence
Toggle Bit (R/Reset)
Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data
Packet Toggle bit by writing "1" to this bit (this bit goes to "0").
Endpoint 2 Payload Register (F6h, 76h)
Maximum Packet Size (R/W)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
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