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| 型號： | MCP18480T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 871K |
| 描述： | IC HOT SWAP CTRLR -48V 20SSOP |
| 標準包裝： | 1,600 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | IP 電話，LAN 網(wǎng)絡(luò)供電，網(wǎng)絡(luò)路由器和交換機 |
| 內(nèi)部開關(guān)： | 無 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
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?2003 Microchip Technology Inc.
DS20091B-page 43
MCP18480
5.0 POWER-UP
5.1
V
POS
and V
NEG
Connection
For proper system operation, it is required that the sys-
tem ground and the V
NEG
pin have a solid connection
before voltages are applied to any logic on the board.
5.2
The Board Circuitry
After the MCP18480 has good voltages on the V
POS
and V
NEG
pins, the board may have voltages applied to
any of the other signals (a good voltage on V
POS
indi-
cates a good voltage on the system ground). The
MCP18480 will start to source a small current to the
external MOSFET to begin powering the board. This
will turn on the MOSFET starting to power the external
circuitry (load) of the board. The current from the GATE
pin (into the external MOSFET) increases as the V
DS
of
the MOSFET decreases. When the VDS of the MOS-
FET is below the voltage determined by the two resis-
tors on the DRAIN
TH
pin (R
DRAIN1
and R
DRAIN2
), and
the voltage on the GATE pin is greater than 8V, the
PWRGOOD pin is active.
6.0 INTERNAL SIGNAL
DESCRIPTIONS
The figure on page 2 illustrates a block diagram of the
MCP18480. Between the functional blocks, there are
some signals that have been named. These signals are
briefly explained in Section 6.1 thru Section 6.7.
6.1
Undervoltage Active
A signal that indicates (when low) that System Ground
- V
NEG
is less then the minimum voltage.
6.2
Overvoltage Active
A signal that indicates (when low) that System Ground
-V
NEG
is greater then the maximum voltage.
6.3
LATCHOFF
A signal that controls the GATE pin due to a timeout of
the current-limiting timer.
6.4
Current Limit TIMER
A signal that controls the reduction of source current on
the GATE pin and starts the voltage ramp of the current
limit timer.
6.5
Current Limit Feedback
A voltage that is proportional to the V
DS
of the external
MOSFET to set a trip point for current-limiting.
6.6
TIMEOUT
A signal that indicates the completion of the foldback
time and is used to start the latchoff time.
6.7
Circuit Breaker
A signal that immediately causes the GATE pin output
to be driven to V
NEG
upon the detection of excessive
current in the external FET.
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