參數(shù)資料
型號： MCP18480T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 37/64頁
文件大?。?/td> 871K
描述： IC HOT SWAP CTRLR -48V 20SSOP
標(biāo)準(zhǔn)包裝： 1,600
類型： 熱交換控制器
應(yīng)用： IP 電話，LAN 網(wǎng)絡(luò)供電，網(wǎng)絡(luò)路由器和交換機(jī)
內(nèi)部開關(guān)： 無
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
?2003 Microchip Technology Inc.
DS20091B-page 37
MCP18480
OVO
17
I
A
Overvoltage detect.
Typically for normal operation. This pin is tied to V
NEG
.
This feature allows the overvoltage detection input to monitor an over-
voltage condition across the power module. The voltage is sensed at
the drain of the external MOSFET. The voltage across the load is inter-
nally determined based upon:
"  The voltage difference between system ground and the voltage
on the V
NEG
 pin
"  The voltage difference between the drain of the external FET and
the voltage on the V
NEG
 pin
An external resistor divider network (R
OVO1
 and R
OVO2
) is attached
between the drain of the external MOSFET and the V
NEG
 pin (R
OVO1
is connected between the drain of the external MOSFET and the OVO
pin, while R
OVO2
 is connected between the OVO pin and the V
NEG
pin).
When the voltage across the external MOSFET (source-to-drain)
equals system ground voltage (- V
NEG
 +), the maximum desired load
voltage, the GATE pin is forced to the voltage on the V
NEG
  pin
(disabling the external MOSFET).
To detect Overvoltage on the board (instead of the load) directly,
connect the OVO pin to the V
NEG
 pin.
PWRGOOD
18
O
D
Power Good indicator.
This state of the output is determined by four conditions. These are:
"  Undervoltage
"  Overvoltage
"  Current Limit
"  External FET is fully-enhanced (from DRAIN
TH
 pin on power-up)
PWRGOOD is a CMOS logic voltage (V
NEG
 or V
NEG
+12V).
PWRGOOD is active when the device has completed power-up and
the system is neither in an Undervoltage or Overvoltage condition.
Connecting the R
ISET
 pin to the V
NEG
 pin configures the PWRGOOD
pin to be active high. Connecting the R
ISET
 pin to the V
REF
 pin config-
ures the PWRGOOD pin to be active low.
ENABLE
19
I
TTL    Enable Gate driver.
Used to enable the GATE pin and assert the PWRGOOD pin. The
ENABLE pin is active-high and is internally pulled up to 5V. This pin is
pulled low by the user to clear the current limit latch when a current-
limit fault occurs with RESTART
 high, or to disable the GATE pin.
H = Enable the GATE and PWRGOOD pins.
L = Disables the GATE pin, deasserts the PWRGOOD pin and clears
current limit latch.
When the ENABLE pin is high, fault conditions will disable the GATE
pin and deasserts the PWRGOOD pin.
TABLE 3-1:
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number
Pin
Direction
Buffer
Type
Description
SSOP
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
O = Output
P = Power
CMOS = CMOS-compatible input
A = Analog
D = Digital
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