參數(shù)資料
型號： MCP18480T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 33/64頁
文件大?。?/td> 871K
描述： IC HOT SWAP CTRLR -48V 20SSOP
標(biāo)準(zhǔn)包裝： 1,600
類型： 熱交換控制器
應(yīng)用： IP 電話，LAN 網(wǎng)絡(luò)供電，網(wǎng)絡(luò)路由器和交換機(jī)
內(nèi)部開關(guān)： 無
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
?2003 Microchip Technology Inc.
DS20091B-page 33
MCP18480
3.0    PIN DESCRIPTIONS
TABLE 3-1:
MCP18480 PIN DESCRIPTIONS
Pin Name
Pin
Number
Pin
Direction
Buffer
Type
Description
SSOP
V
POS
1
I
P
Positive supply input.
Internal Shunt Regulator connected between V
POS
 and V
NEG
 limits the
potential to 12V between these two pins. A series resistor must be
placed on the V
POS
 pin to limit the current into the device.
OV
TH
2
I
A
Overvoltage protection threshold.
An external resistor divider network is connected to this input pin to
program the overvoltage protection threshold. The selected external
resistor values for the OV
TH
 to system ground and OV
TH
 to V
NEG
 resis-
tors should have currents in the 1 mA range. A typical Overvoltage
threshold is -76V. Internal hysteresis in the overvoltage input compar-
ator will allow proper operation once V
NEG
 falls below the selected
threshold.
UV
TH
3
I
A
Undervoltage lockout threshold.
An external resistor divider network is connected to this input pin to
program the undervoltage lockout threshold. If the voltage on UV
TH
 is
less than V
NEG
 + 2.5V, the undervoltage comparator will trip, indicating
an Undervoltage condition.
An external hysteresis resistor can be used to set the high-to-low
(V
THF
) threshold below the low-to-high (V
THR
) threshold. For telecom
network equipment, it is desirable to have shutdown occur at -38.5V
and the startup set at -43.0V.
UV
HYS
4
I
A
Undervoltage internal comparator hysteresis.
An external resistor is connected between this input to the UV
TH
 input
pin to adjust the hysteresis of the internal Undervoltage comparator.
Since it is desirable to shut down at -38.5V and restart at -43.0V in
telecom switch equipment.
UV
D
5
I/O
A
Undervoltage event delay.
An external capacitor is connected to this input pin to set the delay
between when the UV
TH
 pin drops below the trip point specified by the
voltage on the V
REFIN
  pin and when the system shutdown occurs
(causing the PWRGOOD pin to be driven to an inactive level and the
GATE pin to be pulled to the V
NEG
 pin voltage level). The UV
D
 pin
sources a current equivalent to the I
ISET
 (in typical applications, the
I
ISET
  current equals 10 礎(chǔ)), which charges this external capacitor
while an internal comparator compares this voltage on the UV
D
 pin to
|V
REFIN
|/2.
Typically, for telecom equipment, the system is expected to shut down
when the input voltage falls below -38.5V (?.0V DC) for greater than
100 ms.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
O = Output
P = Power
CMOS = CMOS-compatible input
A = Analog
D = Digital
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