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| 型號： | MCP18480T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 35/64頁 |
| 文件大?。?/td> | 871K |
| 描述： | IC HOT SWAP CTRLR -48V 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | IP 電話，LAN 網(wǎng)絡(luò)供電，網(wǎng)絡(luò)路由器和交換機(jī) |
| 內(nèi)部開關(guān)： | 無 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
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?2003 Microchip Technology Inc.
DS20091B-page 35
MCP18480
TIMER
10
I
A
Current Limit Timer.
The value of the external capacitor (C
TIMER
) connected to the TIMER
pin sets the two time periods used during a current-limit event. These
are:
" The time that the GATE pin will limit the current through the
external FET
" The time that the GATE pin will disable the external FET
During current limit, a pull-up current source charges up the external
capacitor. Until the voltage on the TIMER pin reaches V
REFIN
/2, the
GATE pin is driven to maintain a reduced current flow determined by
the V
DS
of the external FET.
While the capacitor is being discharged by the pull-down current (pull-
up current is off), the GATE pin is at V
NEG
and the PWRGOOD pin is
deasserted. When the TIMER voltage falls below approximately
100 mV, the GATE pin turns on, if the RESTART
pin is low, to reset the
internal fault latch. If the RESTART
pin is high, the GATE pin remains
off until the ENABLE pin is forced low. It is then forced high or the
RESTART
pin is forced low (asserted).
The PWRGOOD pin reasserts after the voltages on the DRAIN
TH
and
GATE pins meet the appropriate conditions.
The TIMER pin pull-up current is proportioned to the I
ISET
current
(approximately a multiple of 16).
V
NEG
11
I
P
Negative supply input.
The negative voltage applied to the board by the backplane (typically
the most negative voltage in the system).
R
DISCH
12
I
A
External MOSFET activation delay.
An external resistor (R
RDISCH
) is connected between the R
DISCH
pin
and the V
NEG
pin and is used to set the delay between the deactivation
and activation of the external pass MOSFET during a current-limit
event. The delay is set by the values of the external capacitor (C
TIMER
)
and the external resistor (R
RDISCH
). The formulas are:
T
DEACT
= (C
TIMER
x R
ISET
) / 16
T
ACT
= (9.2 x R
RDISCH
x C
TIMER
)
TABLE 3-1:
MCP18480 PIN DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number
Pin
Direction
Buffer
Type
Description
SSOP
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
O = Output
P = Power
CMOS = CMOS-compatible input
A = Analog
D = Digital
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