參數(shù)資料
型號： MCF53016CMJ240J
廠商： Freescale Semiconductor
文件頁數(shù)： 60/62頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5301x
核心處理器： Coldfire V3
芯體尺寸： 32-位
速度： 240MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 83
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 緩存
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤
Hardware Design Considerations
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
7
Figure 3. Supply Voltage Sequencing and Separation Cautions
3.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause all pad output drivers
connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up
before IVDD must power up. IVDD should not lead the EVDD, SDVDD or PVDD by more than 0.4V during power ramp up or
there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1
microsecond to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1.
Use 1 microsecond or slower rise time for all supplies.
2.
IVDD/PVDD and EVDD/SDVDD should track up to 0.9V and then separate for the completion of ramps with
EVDD/SDVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage
regulator.
3.3.2
Power Down Sequence
If IVDD/PVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance
state. There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. IVDD should
not lag EVDD, SDVDD, or PVDD going low by more than 0.4V during power down or there will be undesired high current in
the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
Drop IVDD/PVDD to 0V.
2.
Drop EVDD/SDVDD supplies.
EVDD, USBVDD (3.3V)
IVDD, PVDD
Time
3.3V
1.2V
0
D
C
P
o
w
e
rSup
p
ly
V
o
ltage
Notes:
1 IV
DD should not exceed EVDD, SDVDD or PVDD by more than 0.4V at any time, including power-up.
2 Recommended that IV
DD/PVDD should track EVDD/SDVDD up to 0.9V then separate for completion of ramps
3 Input voltage must not be greater than the supply voltage (EV
DD, SDVDD, IVDD, or PVDD) by more than 0.5V
at any time, including during power-up.
4 Use 1 microsecond or slower rise time for all supplies.
1
2
2.5V
Supplies Stable
SDVDD (2.5V - DDR)
1.8V
SDVDD (1.8V - DDR)
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