參數(shù)資料
型號(hào)： MCF53016CMJ240J
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 16/62頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5301x
核心處理器： Coldfire V3
芯體尺寸： 32-位
速度： 240MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 83
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 緩存
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤(pán)
Preliminary Electrical Characteristics
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
23
Figure 9. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
5.4.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V
or 3.3V) and EVDD are specified relative to IVDD.
5.4.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers
connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up
before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up,
or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than
500 us to avoid turning on the internal ESD protection clamp diodes.
5.4.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high
impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power
down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be
undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
Drop IVDD/PLLVDD to 0 V.
2.
Drop EVDD/SDVDD supplies.
Board EVDD
0
Ω
0.1 F
USB VDD Pin
10 F
GND
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