參數(shù)資料
型號: MCF53016CMJ240J
廠商: Freescale Semiconductor
文件頁數(shù): 38/62頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝: 450
系列: MCF5301x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 83
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 緩存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Preliminary Electrical Characteristics
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
43
5.17
SIM Electrical Specifications
Each SIM card interface consist of a total of 12 pins (two separate ports of six pins each. Mostly one port with 5 pins is used).
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM
card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work
with CLK equal to 16 times the data rate on TX/RX pins.
There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used
by the SIM card to recover the clock from the data, like a standard UART. All six (or five when a bidirectional TXRX is used)
of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between
the signals in normal mode. However, there are some in reset and power down sequences.
5.17.1
General Timing Requirements
Figure 30 shows the timing of the SIM module, and Table 29 lists the timing parameters.
Figure 30. SIM Clock Timing Diagram
5Power Up Time
250
ms
6
Supply Current
100
200
mA
Bus Signal Line Load
7
Pull-up Resistance
47
10
100
kohm
Internal PU
8
Open Drain Resistance
NA
kohm
For MMC cards only
Open Drain Signal Level
For MMC cards only
9
Output High Voltage
VDD – 0.2
V
IOH = –100 A
10
Output Low Voltage
0.3
V
IOL= 2 mA
Bus Signal Levels
11
Output HIGH Voltage
0.75 x VDD
—V
IOH = –100 A @VDD min
12
Output LOW Voltage
0.125 x VDD
V
IOL = 100 A @VDD min
13
Input HIGH Voltage
0.625 x VDD
VDD + 3
V
14
Input LOW Voltage
VSS – 0.3
0.25 x VDD
V
Table 28. MMC/SD Interface Electrical Specifications (continued)
Num
Parameter
Design
Value
Min
Max
Unit
Condition/Remark
SIM_CLK
Srise
Sfall
1/Sfreq
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