參數(shù)資料
型號: MCF53016CMJ240J
廠商: Freescale Semiconductor
文件頁數(shù): 42/62頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB 256MAPBGA
標準包裝: 450
系列: MCF5301x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB,USB OTG
外圍設備: DMA,PWM,WDT
輸入/輸出數(shù): 83
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 緩存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Preliminary Electrical Characteristics
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
47
Table 32 shows the voice codec general specifications.
5.19.1
Voice Codec ADC Specifications
Voice coding function includes a 50 kHz second-order, low-pass anti-aliasing filter, an analog-to-digital converter, digital filters
for decimation, band-passing, frequency ripple compensation, and DSP interface logic. The audio input A/D converter converts
the incoming signal to 13-bit two’s-compliment linear PCM words at an 8 or 8.1 kHz rate. Following the A/D converter, the
signal is digitally filtered, low-pass, and selectable high-pass. Table 33 shows the voice coding specifications.
Table 32. Voice Codec General Specifications
Parameter
Condition
Min
Typ
Max
Units
CODEC Input clock CODEC_CLK
VCLK[2:0]=0
VCLK[2:0]=1,2
VCLK[2:0]=3
VCLK[2:0]=4
VCLK[2:0]=5
VCLK[2:0]=6
VCLK[2:0]=7
16.8
19.44
20.0
24.0
26.0
28.0
30.0
MHz
VAG input Voltage
No Load,
AVDD (CODEC_REGBYP) =
2.5V
1.225
1.325
1.425
V
Ref_Codec_p
TBD
1.665
TBD
V
Ref_Codec_n
TBD
0.985
TBD
V
VAG External Cap
0.1
μF
avoco_ref_codec_p External Cap
0.1
μF
avoco_ref_codec_n External Cap
0.1
μF
avoco_vagout_codec External Cap
0.1
μF
Codec Analog Supply Current
(includes Rx and Tx paths)
AVDD (CODEC_REGBYP) =
2.5V, operational
—5
6
mA
Power-down mode
5
μA
Codec Digital Supply Current1
1 More accurate estimation will be given after some progress in design.
Operational mode
1
mA
Response to input ON/OFF
(settling time at turn on)
——
1
ms
Table 33. Voice Codec ADC Specifications1
Parameter
Condition
Min
Typ
Max
Units
Power Supply Rejection Ratio
with respect to
AVDD (CODEC_REGBYP)2
20Hz to 100kHz,
with 100 mVpp noise applied to AVDD,
with an external VAG cap
50
60
dB
Peak Input
(+3dBm0)3 on an individual differential
pin (ADC_P or ADC_M)
VAG–0.34
VAG+0.34
V
Tx AC Input Impedance
f=1.02kHz
100
k
Ω
Absolute Gain
0dBm0@1.02kHz
–1.0
1.0
dB
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