參數(shù)資料
型號: MCF53016CMJ240J
廠商: Freescale Semiconductor
文件頁數(shù): 31/62頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB 256MAPBGA
標準包裝: 450
系列: MCF5301x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB,USB OTG
外圍設備: DMA,PWM,WDT
輸入/輸出數(shù): 83
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 緩存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Preliminary Electrical Characteristics
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
37
5.13
Fast Ethernet AC Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
5.13.1
Receive Signal Timing Specifications
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices.
Figure 23. MII Receive Signal Timing Diagram
5.13.2
Transmit Signal Timing Specifications
Table 21. Receive Signal Timing
Num
Characteristic
MII Mode
RMII Mode
Unit
Min
Max
Min
Max
E1
RXD[n:0], RXDV, RXER to RXCLK setup1
1 In MII mode, n = 3; In RMII mode, n = 1
5—4—
ns
E2
RXCLK to RXD[n:0], RXDV, RXER hold1
5—2—
ns
E3
RXCLK pulse width high
35%
65%
35%
65%
RXCLK period
E4
RXCLK pulse width low
35%
65%
35%
65%
RXCLK period
Table 22. Transmit Signal Timing
Num
Characteristic
MII Mode
RMII Mode
Unit
Min
Max
Min
Max
E5
TXCLK to TXD[n:0], TXEN, TXER invalid1
1 In MII mode, n = 3; In RMII mode, n = 1
5—5—
ns
E6
TXCLK to TXD[n:0], TXEN, TXER valid1
25
10
ns
E7
TXCLK pulse width high
35%
65%
35%
65%
tTXCLK
E8
TXCLK pulse width low
35%
65%
35%
65%
tTXCLK
Valid Data
RXCLK (Input)
RXD[n:0]
RXDV,
RXER
E3
E4
E1
E2
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