參數(shù)資料
型號(hào): MCF53016CMJ240J
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 28/62頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝: 450
系列: MCF5301x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 83
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 緩存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
34
5.10
USB On-The-Go
The MCF53017 device is compliant with industry standard USB 2.0 specification.
5.11
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 17. SSI Timing - Master Modes1
1 All timings specified with a capactive load of 25pF.
Num
Description
Symbol
Min
Max
Units
Notes
S1
SSI_MCLK cycle time
tMCLK
8
× t
SYS
—ns
2
2 SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
S2
SSI_MCLK pulse width high / low
45%
55%
tMCLK
S3
SSI_BCLK cycle time
tBCLK
8
× t
SYS
—ns
3
3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does
not exceed 4 x fSYS.
S4
SSI_BCLK pulse width
45%
55%
tBCLK
S5
SSI_BCLK to SSI_FS output valid
15
ns
S6
SSI_BCLK to SSI_FS output invalid
0
ns
S7
SSI_BCLK to SSI_TXD valid
15
ns
S8
SSI_BCLK to SSI_TXD invalid / high impedence
–2
ns
S9
SSI_RXD / SSI_FS input setup before SSI_BCLK
10
ns
S10
SSI_RXD / SSI_FS input hold after SSI_BCLK
0
ns
Table 18. SSI Timing — Slave Modes1
1 All timings specified with a capactive load of 25pF.
Num
Description
Symbol
Min
Max
Units
Notes
S11
SSI_BCLK cycle time
tBCLK
8
× t
SYS
—ns
S12
SSI_BCLK pulse width high / low
45%
55%
tBCLK
S13
SSI_FS input setup before SSI_BCLK
10
ns
S14
SSI_FS input hold after SSI_BCLK
2
ns
S15
SSI_BCLK to SSI_TXD / SSI_FS output valid
15
ns
S16
SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
0—
ns
S17
SSI_RXD setup before SSI_BCLK
10
ns
S18
SSI_RXD hold after SSI_BCLK
2
ns
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