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參數(shù)資料
| 型號： | MC9328MX21DVG |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, MICROPROCESSOR, PBGA289 |
| 封裝： | 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, MAPBGA-289 |
| 文件頁數(shù)： | 85/106頁 |
| 文件大?。?/td> | 1932K |
| 代理商： | MC9328MX21DVG |
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MC9328MX21 Product Preview, Rev. 1.1
8
Freescale Semiconductor
Signal Descriptions
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [17:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals
are multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is
multiplexed with BMI_WRITE of BMI. LD[16] signal is multiplexed with BMI_READ_REQ of BMI
and EXT_DMAGRANT signals.
FLM_VSYNC
(or simply referred
to as VSYNC)
Frame Sync or Vsync—This signal also serves as the clock signal output for gate
driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with
BMI_RXF_FULL and BMI_WAIT of the BMI.
LP_HSYNC (or simply
referred to as HSYNC)
Line Pulse or HSync
LSCLK
Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI.
OE_ACD
Alternate Crystal Direction/Output Enable.
CONTRAST
This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed
with the BMI_READ from BMI.
SPL_SPR
Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
PS
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed
with the SLCDC1_CS.
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated
signal). This signal is multiplexed with the SLCDC1_RS.
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal
is multiplexed with SLCDC1_D0.
Smart LCD Controller
SLCDC1_CLK
SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These
are SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.
SLCDC1_CS
SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are PS and SD2_CMD signals of LCDC and SD2, respectively.
SLCDC1_RS
SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.
SLCDC1_D0
SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is
inactive when a parallel data interface is used.
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
相關PDF資料 |
PDF描述 |
|---|---|
| MC9328MXLCVM15R2 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MXLDVM15 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MXLCVM15 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MC9328MXLDVP15R2 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA225 |
| MC9328MXLVP15R2 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA225 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9328MX21DVH | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21DVK | 功能描述:處理器 - 專門應用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21DVKR2 | 功能描述:處理器 - 專門應用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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