參數(shù)資料
型號: MC9328MX21DVG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, MAPBGA-289
文件頁數(shù): 39/106頁
文件大?。?/td> 1932K
代理商: MC9328MX21DVG
MC9328MX21 Product Preview, Rev. 1.1
38
Freescale Semiconductor
Specifications
3.12.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 26. The symbols for Figure 26 through
Figure 30 are defined in Table 25.
5a
Input hold time3
—10/30 cards
5.7/5.7
5/5
ns
5b
Input setup time3
—10/30 cards
5.7/5.7
5/5
ns
6a
Output hold time3
—10/30 cards
5.7/5.7
5/5
ns
6b
Output setup time3
—10/30 cards
5.7/5.7
5/5
ns
7
Output delay time3
0
16
0
14
ns
1. CL 100 pF / 250 pF (10/30 cards)
2. CL 250 pF (21 cards)
3. CL 25 pF (1 card)
Table 25. State Signal Parameters for Figure 26 through Figure 30
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC
Cyclic redundancy check bits (7 bits)
E
End bit (1)
Table 24. SDHC Bus Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Min
Max
Min
Max
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