參數(shù)資料
型號: MC9328MX21DVG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, MAPBGA-289
文件頁數(shù): 38/106頁
文件大?。?/td> 1932K
代理商: MC9328MX21DVG
Specifications
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
37
3.12
Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/
SD module (inner system) and the application (user programming).
Figure 25. Chip-Select Read Cycle Timing Diagram
Table 23. SLCDC Parallel Transfers Timing
Symbol
Description
Minimum
Maximum
Unit
T1
Pixel clock period
23
962
ns
T2
Data setup time
5
ns
T3
Data hold time
5
ns
T4
Register select setup time
5
ns
T5
Register select hold time
5
ns
Table 24. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Min
Max
Min
Max
1
CLK frequency at Data transfer Mode (PP)1
—10/30 cards
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
0
400
0
400
KHz
3a
Clock high time1
—10/30 cards
6/33
10/50
ns
3b
Clock low time1
—10/30 cards
15/75
10/50
ns
4a
Clock fall time1
—10/30 cards
10/50 (5.00)3
10/50
ns
4b
Clock rise time1
—10/30 cards
14/67 (6.67)3
10/50
ns
Bus Clock
5b
6b
6a
7
5a
4a
3a
CMD_DAT Input
CMD_DAT Output
4b
3b
Valid Data
1
2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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