參數(shù)資料
型號(hào): MC9328MX21DVG
廠(chǎng)商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, MAPBGA-289
文件頁(yè)數(shù): 74/106頁(yè)
文件大?。?/td> 1932K
代理商: MC9328MX21DVG
Signal Descriptions
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
7
Clocks and Resets
EXTAL26M
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal
oscillator circuit is shut down.
XTAL26M
Oscillator output to external crystal
EXTAL32K
32 kHz crystal input
XTAL32K
Oscillator output to 32 kHz crystal
CLKO
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal
clock selection.
EXT_48M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module, SDRAMC module, and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted
from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by
an external RC circuit designed to detect a power-up event.
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, leave these signals as no
connects.
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
TEST_WB[2:0]
These are special factory test signals. However, these signals are also multiplexed with GPIO
PORT E as well as alternate keypad signals. If not utilizing these signals for GPIO functionality or
for it’s other multiplexed function, then configure as GPIO input with pull up enabled, and leave as
a no connect.
TEST_WB[4:3]
These are special factory test signals. To ensure proper operation, leave these signals as no
connects.
WKGD
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising
edge of TCK.
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be
pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal
test purposes only.
RTCK
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is
multiplexed with OWIRE, hence utilizing OWIRE will render RTCK unusable and vice versa.
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC9328MX21DVH 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:i.MX family of microprocessors
MC9328MX21DVK 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21DVK 制造商:Freescale Semiconductor 功能描述:Microprocessor
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