參數(shù)資料
型號: MC9328MX21DVG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, MAPBGA-289
文件頁數(shù): 56/106頁
文件大小: 1932K
代理商: MC9328MX21DVG
Specifications
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
53
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated
clock mode, the clock functions only during transmission. The internal and external clock timing diagrams
are shown in Figure 42 through Figure 45 on page 54.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3.
Note: SRXD input in synchronous mode only.
Figure 42. SSI Transmitter Internal Clock Timing Diagram
Figure 43. SSI Receiver Internal Clock Timing Diagram
CK Output
FS (bl) Output
FS (wl) Output
1
2
6
8
10
11
STXD Output
SRXD Input
32
31
4
12
CK Output
FS (bl) Output
FS (wl) Output
3
7
SRXD Input
13
14
1
5
9
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