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參數(shù)資料
| 型號(hào)： | MC92602ZTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | MAPBGA-196 |
| 文件頁數(shù)： | 9/98頁 |
| 文件大?。?/td> | 896K |
| 代理商： | MC92602ZTA |
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MOTOROLA
Chapter 1. Introduction
1-1
Chapter 1
Introduction
This reference manual explains the functionality of the MC92602 Quad 1.25 Gbaud
Reduced Interface SERDES transceiver and enables its use by software and hardware
developers. The audience for this publication, therefore, consists of hardware designers and
application programmers who are building data path switches and high-speed backplane
intercommunication applications. The remainder of this document will refer to the term
reduced interface as DDR.
1.1
Overview
The MC92602 is a high-speed, full-duplex, serializer/deserializer (SERDES) data interface
device that can be used to transmit data between chips across a board, through a backplane,
or through cabling. The MC92602 has four transceivers that transmit and receive coded
data at a rate of 1.0 gigabit per second (Gbps) through each 1.25 gigabaud link. The
MC92602 is designed specically for high-density board applications where reduction of
interface signals is a primary concern.
The MC92602 is built upon the proven transceiver technology in the Quad MC92600
device and is carefully designed for low power consumption. Its 0.25
CMOS
implementation nominally consumes approximately 1.2 Watts with all links operating at
full speed.
Signal I/O count is reduced relative to the MC92600 device by operating the parallel
interfaces at 125 MHz Double Data Rate (DDR) 4-bits wide per channel, per direction.
HSTL class-I source terminated I/O is an accepted signalling method for 125 MHz DDR
data for FR-4 board traces up to 8 inches. The MC92602 also includes the addition of
transmit FIFOs and source-synchronous transmit clocks per channel to further simplify
interfacing. This aggressive signaling scheme and packaging in a 196 pin ne pitch BGA
offers excellent board density without making unreasonable signal integrity demands of the
ASIC device to which it interfaces.
An IEEE Std 802.3 - 2002 compatibility mode has been included to enable non-intrusive
operation with packet streams. And nally, IEEE Std 1149.1 JTAG boundary scan and
built in PRBS generator/analyzers are provided for board test support.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC92603VF | 功能描述:IC TXRX ETH QUAD GIG 256-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92610 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES |
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