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參數(shù)資料
| 型號： | MC92602ZTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | MAPBGA-196 |
| 文件頁數(shù)： | 33/98頁 |
| 文件大?。?/td> | 896K |
| 代理商： | MC92602ZTA |
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MOTOROLA
Chapter 3. Receiver
3-9
Functional Description
3.3.5
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the Transition Tracking Loop and
decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of
error checking. First it checks that all characters are a legal member of the 8B/10B coding
space. The decoder also checks for running disparity errors. If the running disparity exceeds
the limits set in the 8B/10B coding standard then a disparity error is generated.
An illegal character or disparity error results in a “Code Error” or “Disparity Error” being
reported as described in Section 3.3.6.3. It is difcult to determine the exact byte that
causes a disparity error, so the error should not be associated with a particular received byte.
It is rather a general indicator of the improper operation of the link. Its intended use is for
the system to monitor link reliability.
The 8B/10B decoder is bypassed when operating in Ten-Bit Interface mode (TBIE set
high.)
NOTE
8B/10B coding is meant only to improve data transmission
characteristics and is not a good error detection code. Many
8B/10B characters alias to other valid 8B/10B characters in the
presence of bit errors. Error detection and correction
techniques must be applied outside of the MC92602 if better
than 10-12 bit error rate is required.
3.3.6
Receiver Interface
Data in the alignment FIFO is presented at the Receiver Interface as double data rate, DDR,
on the rising and falling edge of the appropriate receiver clock, RECV_x_CLK. Along with
the data, information is also provided on the status of the link. Table 3-1 describes each of
the signals involved in receiver operation.
Recovered Clock
RCCE
n/a
Does not affect word synchronization.
Receiver A recovered
Clock select
RECV_REF_A
High
(if RCCE is high)
RECV_REF_A must be high if RCCE is enabled. The
receiver A’s recovered clock must be used for all
receivers.
The data at the receiver interfaces will be skewed if the
individual receiver recovered clocks are used to time
the receiver interfaces.
Half-Speed Enable
HSE
n/a
Does not affect word synchronization.
Table 3-3. Word Synchronization Settings (continued)
Mode
Signals
Recommended
State
Description
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| MC92603VF | 功能描述:IC TXRX ETH QUAD GIG 256-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:25 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92603VM | 功能描述:IC ETH TXRX QUAD GIG 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:25 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| MC92610 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 3.125 Gbaud SERDES |
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