參數(shù)資料
型號(hào)： MC92602ZTA
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： MAPBGA-196
文件頁(yè)數(shù)： 21/98頁(yè)
文件大小： 896K
代理商： MC92602ZTA
2-6
MC92602 SERDES Reference Manual
MOTOROLA
Functional Description
2.3.1.3
Transmit Interface Clock Conguration
The transmitter data interface operates at high frequency (up to 125MHz double data rate).
Data is clocked into the transmitter on both the rising and falling edges of the transmit
clock. In order to ease development of devices that interact with the MC92602, all of its
data interfaces are source-synchronous. The data for each transmitter has its own dedicated
clock input. This allows the clock at the source of the data to be routed with the data
ensuring matched delay and timing. However, if per-transmitter clock sources are not
available or deemed unnecessary, all transmitters may be clocked by a common clock
source. This is enabled by asserting XMIT_REF_A high. When XMIT_REF_A is high, the
XMIT_A_CLK becomes the interface clock for all active channels.
The conguration settings of the MC92602 affect the legal range of clock frequencies at
which it may be operated. Table 5-1 shows legal transmit interface clock frequencies for all
modes of operation. All transmit interface clock inputs, XMIT_x_CLK, and the PLL
reference clock, REF_CLK, inputs must have identical frequencies. The transmit data
interface tolerates +180o of transmit interface clock phase drift relative to the PLL reference
clock.
2.3.2
8B/10B Encoder Operation
The 8B/10B Encoder encodes 8-bit data/control from the input register into 10-bit
transmission characters. The Fibre Channel 8B/10B coding standard is followed [1,2].
Running disparity is maintained and the appropriate transmission characters are produced,
maintaining DC balance and sufcient transition density to allow reliable data recovery at
the receiver.
The inputs to the 8B/10B Encoder are the data byte (internal Data Bits 7 through 0), special
code signal (K) and transmit idle signal (IDLE).
Data and legal control bytes are coded according to the 8B/10B method. Illegal control
bytes produce unpredictable transmission characters, which may lead to disparity and
coding errors, thereby reducing link reliability.
The 8B/10B encoder produces an Idle character (K28.5) of proper running disparity when
K is high and IDLE is low, as indicated in Table 2-4.
The 8B/10B Encoder is bypassed if TBIE is asserted high.
2.3.3
Transmit Driver Operation
The Transmit Driver drives transmission characters serially across the link. Two bits per
transceiver clock, one each on the rising and falling transceiver clock (rx_clock) edges, are
transmitted differentially from the XLINK_x_P/XLINK_x_N outputs. The internal
rx_clock runs at 625 MHz for 1 Gbps (1.25 Gbaud) operation and 312.5 MHz for 500 Mbps
(625 Mbaud) operation.
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