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參數(shù)資料
| 型號(hào)： | MC92602ZTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | MAPBGA-196 |
| 文件頁數(shù)： | 38/98頁 |
| 文件大小： | 896K |
| 代理商： | MC92602ZTA |
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MOTOROLA
Chapter 3. Receiver
3-13
Functional Description
All receiver channel outputs are source synchronous with their respective RECV_x_CLK
outputs. If the receivers are being operated in word synchronization mode (WSE = high),
the data for all four receivers are timed relative to link A’s recovered clock RECV_A_CLK.
In word synchronization all four clocks are derived from channel A and may be used if
necessary.
When operating in the recovered clock timing mode, the addition or deletion of Idles is
inappropriate.
NOTE
If RCCE is asserted (recovered clock timing mode), the
add/delete idle enable (ADIE) signal must be low.
3.3.7.2
Reference Clock Timing Mode
Data is timed relative to the local reference clock frequency when RCCE is low.
Synchronization between the recovered clock and the reference clock is handled by the
receiver interface. Frequency offset between the transmitter’s reference clock and the
receiver’s reference clock causes overrun/underrun situations. Overrun occurs when the
transmitter is running faster than the receiver. Underrun occurs when the transmitter is
running slower than the receiver.
In an overrun situation, data must be dropped in order to maintain synchronization between
the clock domains. If the control signal, add drop idle enable, ADIE, is asserted high, the
receiver interface searches for a pair of idle bytes to drop when overrun is imminent. Two
idle bytes are dropped to assure that running disparity is not affected. If sufcient idle
patterns are not available to drop, receiver overrun may occur. When overrun occurs, the
“Overrun” error is reported as described in Section 3.3.6.3, for one byte clock period and
one character of data is dropped. An overrun error is also reported if ADI mode is disabled
and overrun occurs, even if Idles are available to drop.
NOTE
The compatibility mode control signal, COMPAT, set high,
instructs the receivers to follow a different set of rules for the
addition and deletion of characters that are non-intrusive to
packet data streams, but still enable the device to maintain
synchronization between the clock domains. See Section 5.4
for more information.
A sufcient number of Idles must be transmitted to guard against overrun. The frequency
of Idles can be computed based upon the maximum frequency offset between transmitter
and receiver in the system. The number of bytes (characters) that can be transmitted
between Idles is:
(2*106 / N) - 1 bytes
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| MC92604VM | 功能描述:IC ETH TXRX DUAL GIG 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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