參數(shù)資料
型號(hào)： MC92602ZTA
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： MAPBGA-196
文件頁(yè)數(shù)： 57/98頁(yè)
文件大?。?/td> 896K
代理商： MC92602ZTA
6-4
MC92602 SERDES Reference Manual
MOTOROLA
System Accessible Test Modes
transmitted are received by the receiver. This allows system logic to use various data
sequences to test the operation of the transceiver.
The loop-back signals are electrically isolated from the XLINK_x_P or XLINK_x_N
output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back
signals still operate normally. When in loop-back mode, the loop-back output enable,
LBOE, signal controls the action of the link output signals. When LBOE is low, the
XLINK_x_P or XLINK_x_N output signals are disabled and are high-impedance. When
LBOE is high, the link output signals continue to operate normally.
The receiver’s link input signals, RLINK_x_P and RLINK_x_N, are electrically isolated
during loop back mode, such that their state does not affect the loop back path.
6.2.2
BIST Sequence System Test Mode
The MC92602’s transmitter has an integrated, 23rd order, Pseudo-Noise (PN) pattern
generator. Stimulus from this generator may be used for system testing. The receiver, has a
23rd order signature analyzer that is synchronized to the incoming PN stream and may be
used to count character mismatch errors relative to the internal PN reference pattern.
This implementation of the 23-bit PN generator and analyzer uses the polynomial:
f = 1 + x5 + x23
The total mismatch error count is reset to zero when BIST mode is entered. The count is
updated continuously while in BIST mode. The value of the count is presented on the
receiver interface signals: RECV_x_3 through RECV_x_0 (as interpreted and shown in
Table 3-4), making up the eight-bit error count, ordered bits 7 through 0, respectively. The
value of the count is sticky in that the count will not wrap to zero upon overow, but rather,
stays at the maximum count value (11111111).
The RECV_x_ERR, RECV_x_K (as interpreted and shown in Table 6-5), have special
meaning during this test mode. They report the status of the receiver and PN analysis logic.
Table 6-5 describes the BIST error codes and their meaning. E0 and K0 are the values on
RECV_x_ERR and RECV_x_K, respectively, on the rising edge of the recovered clock. E1
and K1 are the values of RECV_x_ERR and RECV_x_K, respectively, on the falling edge
of the recovered clock
.
Table 6-5. BIST Error Codes
E0
E1
K0
K1
Description
Low
Don’t care
Don’t care BIST running, no PN mismatch this character.
Low
High
Low
BIST running, PN mismatch error this character.
Low
High
Low
High
Receiver byte/word synchronized, PN analyzer is not locked.
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