參數(shù)資料
型號(hào)： MC92602ZTA
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： MAPBGA-196
文件頁(yè)數(shù)： 47/98頁(yè)
文件大?。?/td> 896K
代理商： MC92602ZTA
MOTOROLA
Chapter 5. System Design Considerations
5-1
Chapter 5
System Design Considerations
This chapter describes general system considerations for the MC92602 Quad DDR,
including device-startup, initialization and the proper use of the conguration and control
signals, the reference clock conguration, and general recommendations.
5.1
Reference Clock Conguration
The clock inputs REF_CLK_P and REF_CLK_N are the differential reference clock inputs
for the MC92602. The frequency of the clock signal applied to these inputs along with the
settings on the conguration inputs determine the speed at which the serial links operate.
Also, the legal ranges of reference clock frequencies vary depending on the conguration
selected. Table 5-1 shows the ranges allowed for each conguration.
NOTE
The device must be reset by setting RESET low, if the reference
clock conguration, HSE, is changed after power-up.
The clock inputs REF_CLK_P and REF_CLK_N are normally driven with a differential
clock source. However, the reference clock may also be driven with a single-ended source.
In this situation, the REF_CLK_P signal is driven by the single-ended clock source and the
REF_CLK_N signal is held at the HSTL reference voltage as dened in Section 5.8. The
REF_CLK_N signal may be connected to its own reference voltage circuit or may share the
reference voltage circuit used for the HSTL_VREF signal, if board layout allows.
Table 5-1. Legal Reference Clock Frequency Ranges
HSE
Reference Frequency
Min (MHz)
Reference Frequency
Max (MHz)
Link Transfer Rate
(Gigabaud)
Low
95.00
135.0
0.95 - 1.35
High
47.50
67.50
0.475 - 0.675
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