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參數(shù)資料
| 型號： | MC8610VT800GZ |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, ROHS COMPLIANT, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 77/96頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | MC8610VT800GZ |
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Hardware Design Considerations
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
79
RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN
are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
Figure 51. Driver Impedance Measurement
Table 60 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD,
105
°C.
3.8
Configuration Pin Muxing
The MPC8610 provides the user with power-on configuration options which can be set through the use of external pull-up or
pull-down resistors of 4.7 k
Ω on certain output pins (see customer visible configuration pins). These pins are generally used as
output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is
asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal
function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k
Ω. This
value should permit the 4.7-k
Ω resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled
only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When
the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal
quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage
level puts the device into the default state and external resistors are needed only when non-default settings are required by the
user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down
resistor should minimize the disruption of signal quality or speed for output pins thus configured.
The platform PLL ratio and e600 core PLL ratio configuration pins are not equipped with these default pull-up devices.
Table 60. Impedance Characteristics
Impedance
Local Bus, DUART, Control,
Configuration, Power
Management
PCI Express
DDR DRAM
Symbol
Unit
RN
43 Target
25 Target
20 Target
Z0
W
RP
43 Target
25 Target
20 Target
Z0
W
OVDD
OGND
Pad
Data
SW1
SW2
RN
RP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8610VT800J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC861P | 制造商:Motorola Inc 功能描述: 制造商:Texas Instruments 功能描述: |
| MC862 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:INTEGRATED CIRCUITS |
| MC862L | 制造商:Motorola Inc 功能描述: |
| MC862P | 制造商:PRISM ELECTRONICS 功能描述:TRIPLE 3 INPUT NAND GATE DTL |
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