參數(shù)資料
型號: MC8610VT800GZ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù): 33/96頁
文件大?。?/td> 1237K
代理商: MC8610VT800GZ
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
39
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H, and FP_H
parameters are programmed via the HSYN_PARA register; and the PW_V, BP_V, and FP_V parameters are programmed via
the VSYN_PARA register.
Figure 14 depicts the synchronous display interface timing for access level, and Table 29 lists the timing parameters.
Figure 14. LCD Interface Timing Diagram—Access Level
NOTE
The DIU_OUT_CLK edge and phase delay is selectable via the Global Utilities CKDVDR
register.
2.9
I2C
This section describes the DC and AC electrical characteristics for the I
2C interfaces of the MPC8610.
2.9.1
I2C DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the I
2C interfaces.
Table 29. LCD Interface Timing Parameters—Access Level
Parameter
Symbol
Min
Typ
Max
Unit
LCD interface pixel clock high time
tCKH
0.35
× tPCP
0.5
× tPCP
0.65
× tPCP
ns
LCD interface pixel clock low time
tCKL
0.35
× tPCP
0.5
× tPCP
0.65
× tPCP
ns
LCD interface pixel clock to ouput valid
tDIUKHOV
——
2
ns
LCD interface output hold from pixel clock
tDIUKHOX
tPCP – 2
ns
Table 30. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OVDD
OVDD +0.3
V
Input low voltage level
VIL
–0.3
0.3
× OVDD
V
Low level output voltage
VOL
00.2
× OVDD
V1
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
050
ns
2
tCKH
DIU_HSYNC
DIU_VSYNC
DIU_DE
DIU_CLK_OUT
tDIUKHOV
tCKL
DIU_LD
tDIUKHOX
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