參數(shù)資料
型號： MC8610VT800GZ
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁數(shù)： 32/96頁
文件大?。?/td> 1237K
代理商： MC8610VT800GZ
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
38
Figure 13 depicts the vertical timing (timing of one frame), including both the vertical sync pulse and the data. All parameters
shown in the diagram are programmable.
Figure 13. TFT DIU/LCD Interface Timing Diagram—Vertical Sync Pulse
Table 28 shows timing parameters of signals presented in Figure 12 and Figure 13.
Table 28. DIU Interface AC Timing Parameters—Pixel Level
Parameter
Symbol
Value
Unit
Notes
Display pixel clock period
tPCP
7.5 (minimum)
ns
1, 2
1 Display interface pixel clock period immediate value (in nanoseconds).
2 Display pixel clock frequency must also be less than or equal to 1/3 the platform clock.
HSYNC width
tPWH
PW_H
× tPCP
ns
HSYNC back porch width
tBPH
BP_H
× tPCP
ns
HSYNC front porch width
tFPH
FP_H
× tPCP
ns
Screen width
tSW
DELTA_X
× tPCP
ns
HSYNC (line) period
tHSP
(PW_H + BP_H + DELTA_X + FP_H)
× tPCP
ns
VSYNC width
tPWV
PW_V
× tHSP
ns
HSYNC back porch width
tBPV
BP_V
× tHSP
ns
HSYNC front porch width
tFPV
FP_V
× tHSP
ns
Screen height
tSH
DELTA_Y
× tHSP
ns
VSYNC (frame) period
tVSP
(PW_V + BP_V + DELTA_Y + FP_H)
× tHSP
ns
Notes:
1
2
3
DELTA_Y
Tpwv
Tbpv
Tsh
Tfpv
DIU_HSYNC
DIU_LD
DIU_VSYNC
DIU_DE
Thsp
1
(Line Data)
Start of Frame
Invalid Data
Tvsp
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC8610VT800J 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
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